1. Field of the Invention
The present invention relates generally to delay reduction for global interconnect by introducing pipelining, and more particularly, to methods for reducing the signal delay violation of clock cycle for signals distributed over long distances between logic blocks of an integrated circuit design.
2. Description of the Related Art
As the scale of integrated circuits continue to grow and the features of process technology continue to shrink, coupled with ever increasing clock frequency, timing has become a more and more dominating factor in global interconnect design. Circuit designers usually use proper planning in logic synthesis, physical floor layout, and calculated placement to ensure that signals at the global integration level can reach their destination within the clock period. However, this may not be possible with new designs using higher clock frequency and new process technology.
Repeater insertion is extensively used to reduce signal delays for interconnects, especially when signals are distributed over long distances on a chip. However, as the signal paths of a global interconnect become longer, the number of repeaters needed for the global interconnect increases. When the number of repeaters inserted for a global interconnect is more than an optimal number, the excessive number of repeaters will cause additional signal delays for the global interconnect due to the intrinsic delay of repeaters, which is undesired.
In order to overcome the repeater delay problems in a global interconnect, a method of concurrent flip-flop (flop) and repeater insertion that uses generalized delay models and multiple types of repeaters and flops was proposed. This method uses flops as clocked repeaters to avoid negative slack during the computation. However, this method does not effectively address the need if the number of flops between any given driver-receiver pair is constrained.
In view of the foregoing, there is a need for a method of flop insertion that will shorten the flop-to-flop signal path in order for signals to meet a cycle time constraint along with a flop stage requirement for the signal path of an interconnect.